mode

POWERDOWN, NORMAL, PDNE, STANDBY.

PDNE means POWERDOWN if not executing a conversion cycle.

clock

This is a constant that specifies the clock division of the master clock. It may be 1,2,4 or 8.

An ADC conversion will require 16 ADC clocks in addition to the selected number of acquisition clocks.

aq

This is a constant that specifies the time available for the input/track hold amplifier to acquire the input signal.

It may be in range from 1-4. 1 Acquisition clock is enough for an impedance up to 8K

tm2

The TIMER2 can be ENABLED or DISABLED. When enabled the timer2 overflow serves as a trigger for the AD conversion.

value

The external trigger may be ENABLED or DISABLED. When enabled the external pin 23 (CONVST) can start the conversion while it is low.

Mode

The DAC can be in 8 bit mode or 12 bit mode. So the parameter may be 8 or 12. Both DACS are set with this parameter.

r0

The DAC0 range can be set to VDD or VREF. With VDD the range is from 0-VDD. For VREF it is 0-VREF.

r1

The DAC1 range can be set to VDD or VREF. With VDD the range is from 0-VDD. For VREF it is 0-VREF

clr0

This parameter when TRUE will clear the DAC0. This will set the output voltage to 0 V.

clr1

This parameter when TRUE will clear the DAC1. This will set the output voltage to 0 V

Sync

May be ENABLED or DISABLED. While enabled the DAC outputs as soon as the DACxL SFR's are written. The user can simutaneously update both DAC's by first updating the DACxL/H SFR's while SYNC is disabled. Both DACs will then update when the SYNC is enabled.

pwr0

This parameter when ON will power ON the DAC0. When OFF the DAC0 is powered OFF.

pwr1

This parameter when ON will power ON the DAC1. When OFF the DAC1 is powered OFF